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G2L: I2C LCD clock too high

Andrei

Hello everyone,

We are currently developing a product using your G2L SoC.

When measuring the I2C2 (LCD) clock, we are measuring 227.3 kHz (with an oscilloscope) instead of the expected 100kHz.

Here is the relevant device tree block:
        i2c2: i2c@10058800 {
            #address-cells = <1>;
            #size-cells = <0>;
            compatible = "renesas,riic-r9a07g044l",
                    "renesas,riic-rz";
            reg = <0 0x10058800 0 0x44>;
            interrupts = <GIC_SPI 366  IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
                     <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&cpg CPG_MOD R9A07G044L_CLK_I2C2>;
            clock-frequency = <100000>;
            resets = <&cpg R9A07G044L_CLK_I2C2>;
            status = "disabled";
        };

In U-boot, we can see:

=> i2c dev 2
Setting bus to 2
=> i2c speed
Current bus speed=100000

We've traced this issue back to drivers/i2c/rzg2l_riic.c, specifically to this:

static int riic_set_clock(struct udevice *dev, int clock)
{
struct riic_priv *priv = dev_get_priv(dev);

priv->base = dev_read_addr_ptr(dev);

switch (clock) {
case 100000:
riic_clear_bit(priv, ICFER_FMPE, RIIC_ICFER);
riic_clear_bit(priv, ICMR1_CKS_MASK, RIIC_ICMR1);
riic_set_bit(priv, ICMR1_CKS(3), RIIC_ICMR1);
riic_write(priv, ICBRH_RESERVED | 23, RIIC_ICBRH);
riic_write(priv, ICBRL_RESERVED | 23, RIIC_ICBRL);
break;
case 400000:
riic_clear_bit(priv, ICFER_FMPE, RIIC_ICFER);
riic_clear_bit(priv, ICMR1_CKS_MASK, RIIC_ICMR1);
riic_set_bit(priv, ICMR1_CKS(1), RIIC_ICMR1);
riic_write(priv, ICBRH_RESERVED | 20, RIIC_ICBRH);
riic_write(priv, ICBRL_RESERVED | 19, RIIC_ICBRL);
break;
case 1000000:
riic_set_bit(priv, ICFER_FMPE, RIIC_ICFER);
riic_clear_bit(priv, ICMR1_CKS_MASK, RIIC_ICMR1);
riic_set_bit(priv, ICMR1_CKS(0), RIIC_ICMR1);
riic_write(priv, ICBRH_RESERVED | 14, RIIC_ICBRH);
riic_write(priv, ICBRL_RESERVED | 14, RIIC_ICBRL);
break;

default:
debug("%s: unsupported clock (%dkHz)\n", __func__, clock);
return -EINVAL;
}

return 0;
}

For the 100000 case, changing CKS from 3 to 4, BRH from 23 to 27 and BRL from 23 to 28, we are able to measure the expected 100kHz.

Why are we measuring these 227,3 kHz with the default values of your BSP?

Thank you and kind regards,

Andrei