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SerDes Quad associated with Port Number - legacy IDT part number 89H48H12G2ZCBLGI

QNguyen

The device’s user manual says the device has quads numbered 0 to 11 and that the quad is normally aligned with port number.  This statement is under the title "SerDes Numbering and Port Association" on page 113 of user manual.

However, this device skips ports 10 and 11 on Fig 4.1 on page 61.  So the question is:

 

What SerDes quad is associated with Port 12 and 13?

Regards,

Quynh

  • 0

    Cold and Hot Ramp failure (same 89H48H12G2ZCBLGI device):

    Questions:

    1. Should transitions from L1 perform the same SerDes recalibration as L0s to ‘resolve’ the ramping issue?
    2. Is there any reasonable way outside of a protocol analyzer to debug what is failing with L1 enabled?
      1. This link is completely on card and failure happens in a thermal chamber. We don’t have a protocol analyzer to support this.
    3. Are there any device settings that could be modified to improve the training or robustness when transitions from L1 to L0?
      1. Would increasing latency timers or other help? Which ones?
  • 0

    QNguyen,

    Le me reach out to our engineering team and see if they have any pointers.  This product is obsolete and there many not be any good information that we can provide, but I will certainly check.

  • 0 in reply to Michael Quirk

    Thanks Michael,

    I've reached out to Renesas FAE (Mark Lissner) for help and he may channel through the same Eng team for support.  Anyway, any help here is much appreciated.

    Rgds.,

    QN

  • +1 in reply to QNguyen

    QNguyen,

    1. The “Introduction” section of the Device User Manual incorrectly states that SerDes and Port numbering is from 0 to 11 for this device. It should have stated: “0 to 9 and 12, 13”.
    2. The rest of the Device User Manual (including the block diagrams, etc) are all correct and use 0-9 & 12, 13.
    3. There are many bond options (package options) created form this single die to offer cost optimized products with various port and lane count configurations. For ease of package substrate routing some ports/serdes are skipped in certain product/package options. This is one such case where port 10 and 11 were skipped and disabled.
    4. You have been made aware of this and we have proceeded with the debug effort of their main issue with the help of Mark Lissner as the FAE and the product line Apps team.