Two key features of the RL78/G12 are its 8-channel 10-bit ADC with a 2.1 μsec conversion time; and a 2-channel DMA controller. Renesas has recently published an application note and a sample application that performs A/D conversion on four channels of analog input voltages, storing the A/D conversion results in the on-chip RAM through the DMA controller.
In addition to the application note you can download example code (ASM and Cubesuite+ project files), which is designed to work with the RL78/G12 target board (QB-R5F1026A-TB) and the Renesas RA78K0R V1.50 assembler. The application note explains the data transfer operation and the example code shows how it’s done.
The application runs the ADC in Scan Mode; it performs A/D conversion on four channels sequentially and repeats this cycle 10 times. The application totals 10 cycles of A/D conversion results for each channel in parallel to A/D conversion and DMA transfer. The number stored in the ADCR register is transferred to RAM each time an A/D conversion end interrupt (INTAD) is generated; a DMA end interrupt is generated when 40 cycles of DMA transfer end. The process then repeats itself.
The application uses the multiplier and divider/multiply-accumulator (MAC) in the multiply-accumulator mode to shorten the time to calculate the total of the A/D conversion results, causing the MAC to shift and accumulate the conversion results. Thus, the buffer is prevented from overrunning in parallel operation. After comparing the totals of the A/D conversion results, on the LED display the application displays the number of the channel that has the largest total of the A/D conversion results.
Figure 1: Outline of A/D conversion and DMA controller operations
For further information check the RL78/G12 Datasheet and User’s Manual.