We have problems while performing the EMC test Burst EN 61000-4-4.
The problems occurs in any voltage even at 500V and while applying the voltage in any of the sources. It does not occur always, is aleatory.
A reset is generated while applying the surge and the reset causes are RAM parity error or (RPERF) illegal memory access (IAWRF).
We are using a RL78G13-100GC.
The microcontroller internal oscillator is used. We have added the external oscillator footprint, because we had great problems in the past with NEC 78K0 KE2 44 pin internal microcontroller.
Does somebody know something about this kind of problems?
When you say you are using RL78G13-100GC, I assume you mean R5F100GC (48pin RL78/G13 with 32KB code flash)
I'm not familiar with EMC test Burst (IEC?) EN 61000-4-4, but it sounds much more severe than ESD HBM (human body model) test.
Have you contacted your local Renesas sales/technical office to see if there is any Renesas-supplied data to show typical results for EMC test Burst EN 61000-4-4?
In general, the circuit board (PCB) copper trace design can affect ESD/EMI/EMC immunity. These points should be analyzed:
1. Length and position of VDD and VSS connection. Common connections of VDD and VSS should be made in a "Star" pattern with heavy traces to Power source and ground.
2. By-pass caps on VDD to VSS, and sometimes on I/O pins can help.
3. REGC pin with typical 0.47uF capacitor is a critical. The REGC connection to 0.47uF should be short and the VSS connection to 0.47uF cap should be short. In some cases a 0.01uF or 0.001uF with low impedance at RF frequencies can be put in parallel with 0.47uF to help reduce EMI.
Also, please see these two Renesas app notes:
R01AN0839EJ0100, Rev.1.00, Oct. 4, 2011, RL78 Family, Notes and Countermeasures Against Noise
R01AN1876EC0100, Rev. 1.00, Feb. 28, 2014, RL78/G14, Recommended PCB Layout for Reducing Noise
Regards,
Mike