• State Verified Answer
  • Replies 7 replies
  • Subscribers 77 subscribers
  • Views 7672 views
  • Users 0 members are here
Options
Related

no UART Communication in UART1 in Renesas RL78G14 RDK board.

hemanth

Hello,

I am using Renesas RL78G14 RDK board.

I downloaded the sample IAR project from below link:
http://in.renesas.com/support/downloads/download_results/C1000000-C9999999/tools/yrdkrl78g14_factory_demo_v39.jsp

I am unable to see UART communication in any mode supported.

I guess it looked like clocking issue.
I found multiple definition for clock freq.

/* YRDKRL78G14.h */
#define RL78_MAIN_SYSTEM_CLOCK          12000000    /* MHz */
#define RL78_SUBSYSTEM_CLOCK            32768       /* kHz */
#define RL78_INTERNAL_LOWSPEED_CLOCK    15000       /* kHz */

/* UART.c */
#define MAIN_SYSTEM_CLOCK        32000000

Could anybody confirm which value needs to be used for baud rate calculation?

Current code uses macro MAIN_SYSTEM_CLOCK

Also if any other issue is suspected in UART in RL78G14 board would really helpful

Thanks!!

regards,
Hemanth

UPDATE:

Enabling of UART-1 Tx & Rx by setting the Register "SS10", causes Higher 7 bits of the serial data register SDR02 & SDR03 to reset. How can i prevent the reset happening?

Parents
  • 0

    Hi Hemanth,

    I'm sorry, but I have not tried the demo that uses "App_PassThroughSPI" mode.

    If the Upper 7-bits(SDR02[15:9] & SDR03[15:9]) are reset (zero) that would set a divide by 2 after the fMCK clock.

    If using option byte 000C2H = 0xE8 (fHOCO = 32MHZ, fIH = 32MHZ) or 0xF8 (fHOCO = 64MHZ, fIH = 32MHZ),

    then fCLK in the SAU0 block = 32MHZ.

    To get 115.2Kbaud, you would use CK00, and SPS0 set to 0x0001 gives fMCK = 16MHZ

    Then, 16MHZ/138 = 115.942Kbaud, which is the closest setting to 115.2Kbaud.

    To get divide by 138, set Upper 7-bits(SDR02[15:9] & SDR03[15:9]) to binary 1000101 (OR the SDR02/SDR03 registers with 0x8A00).

    Do you have the DipSW5, position4 set to ON?  (SW4 ON gives Power to the GainSpan GS1011 module)  For debug mode the DIPSW5 should be set to:

    SW1 ON

    SW2 OFF

    SW3 ON

    SW4 ON

    Have you tried the yrdkrl78g14_factory_demo_v39 in Demo1 mode (pushbutton switches SW1, SW2, SW3 NOT pressed on startup) to see if the basic GainSpan demo of YRDKRL78 sensors (Accelerometer, Temp, Light) works?

    -Mike

Reply
  • 0

    Hi Hemanth,

    I'm sorry, but I have not tried the demo that uses "App_PassThroughSPI" mode.

    If the Upper 7-bits(SDR02[15:9] & SDR03[15:9]) are reset (zero) that would set a divide by 2 after the fMCK clock.

    If using option byte 000C2H = 0xE8 (fHOCO = 32MHZ, fIH = 32MHZ) or 0xF8 (fHOCO = 64MHZ, fIH = 32MHZ),

    then fCLK in the SAU0 block = 32MHZ.

    To get 115.2Kbaud, you would use CK00, and SPS0 set to 0x0001 gives fMCK = 16MHZ

    Then, 16MHZ/138 = 115.942Kbaud, which is the closest setting to 115.2Kbaud.

    To get divide by 138, set Upper 7-bits(SDR02[15:9] & SDR03[15:9]) to binary 1000101 (OR the SDR02/SDR03 registers with 0x8A00).

    Do you have the DipSW5, position4 set to ON?  (SW4 ON gives Power to the GainSpan GS1011 module)  For debug mode the DIPSW5 should be set to:

    SW1 ON

    SW2 OFF

    SW3 ON

    SW4 ON

    Have you tried the yrdkrl78g14_factory_demo_v39 in Demo1 mode (pushbutton switches SW1, SW2, SW3 NOT pressed on startup) to see if the basic GainSpan demo of YRDKRL78 sensors (Accelerometer, Temp, Light) works?

    -Mike

Children