I wasn't sure which forum this question belonged to...
I'm having trouble taking the calculations from AN-860 and applying them to the registers defined in the 8T49N287 datasheet. For example, I'd like to set the upper loop feedback divider to a value of: (4000)/(38.88*2) = 51.440329218107. The document shows this split into an integer portion (51) and a fractional portion times 2^21: (0.440329218107*2^21) = 923437, and says that DSM is sometimes called the M1 divider.
However, the datasheet for 8T49N287 shows a register with the "M1 Feedback Divider Ratio", a 24 bit value, with no description of how the integer and fractional portion should be packed.
I also have a little bit of confusion as there is a feedback divider ratio for using Input Reference 0, and a different ration for Input Reference 1, but there is also a free-running mode where you don't use either reference (just the XTAL). Which M1 register should I use in that case?
The APLL fractional divider is not the same as the M1 divider. The M1 divider is part of the lower loop. See Figure 4 in the App Note.
Regarding your other questions:
However, the datasheet…
However, the datasheet for 8T49N287 shows a register with the "M1 Feedback Divider Ratio", a 24 bit value, with no description of how the integer and fractional portion should be packed. This is not a fractional divider. Please use the GUI as a reference.
In freerun, no input clock is used, so M1 is irrelevant.