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Versa 5 phase noise

We are programming the clock the first time.  Phase noise tested is 10dB worse than the phase noise shown in datasheet for region from 1MHz offset and above (outside the PLL loop).  What could be wrong? Also notice your plot has 15dBm output. Did you use external amplifier?


[locked by: Michael Quirk at 15:27 (GMT 0) on 14 Jul 2022]
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