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ClockMatrix Output Coarse Phase Alignment

Kolja

Hi,

we want to use the 8a34001 system synchronizer in one of our new products. For evaluation we are experimenting with the evaluation board.

We can configure a lot of our desired settings successfully, but we fail to synchronise the output phase of two outputs derived from the same input clock with different FODs. The coarse phase offset between the two output seems to vary randomly between reconfigurations of the parameters.

Our assumption is that the output divders are not synchronised. But we do not understand what is necessary to do that.

The ultimate goal is to have to identical clocks with 10 MHz each that have a programmable phase offset between them.

Beside a short comment in the Timing Commander I could not find any documentation on how to reset the output dividers simultaneosly. 

Do you have any tips for us how to do it?

We would also be willing to pay for an FAE to train us or provide a configuration to us.

Regards,

Kolja

  • 0

    Kolja,

    Would you mind zipping up your .TCS file and attaching it to this forum so that I may review.

  • 0 in reply to Kolja

    Kolja,

    I have escalated this internally to our applications team [ TECHSUPP-6726 ].  I will get back to you when I hear back from them.

  • 0 in reply to Kolja

    Kolja,

    Can you provide a list of inputs, outputs and DPLL bandwidths (if not frequency translation at ~25 Hz).

    Then we will create a TCS with output alignment between channels and provide a method to change the alignment between the outputs via register writes.

  • 0 in reply to Michael Quirk

    We are testing with both our own PCB with an 8A34003 and with your evaluation board with an 8A34001.

    For the tests we are generating the frequency from a crystal connected to OSCI/OSCO. It has 10 MHz at our own PCB and 12,8 MHz at the evaluation board.

    Later it shall be possible to optionally select a 10 MHz single ended clock with 10 MHz on CLK0 or a single ended PPS pulse on CLK1 as a reference. I think we know how to add this, so we can ignore these options for now.

    There is a 10 MHz OCXO connectors to XO_DPLL. 

    Outputs are single ended on Q8 to Q11 on our board. On the evaluation board arbitrary outputs can be used. We ultimately need 4 outputs, but I guess we can extrapolate from a two output example.

    The frequency shall be identical on all  outputs. We are testing with 100 kHz, but it shall later be possible to program it over a wide range of frequencies. 
    The duty cycle will be very low, typically 10ns pulse width, but that shall also be programmable. 

    The phase offset between the outputs shall be programmable in a stepsize as small as possible. 
    I believe that in our configuration the fine adjustment is working but the coarse phase adjustment at the output divides fails to synchronize. But I could be wrong.

    We have not put much thought into the required PLL bandwidth. But the PLL frequency will almost never change, so the bandwidth can be very low. 

    Thank you for your support,

    Kolja

  • 0 in reply to Kolja

    Thank you for your information and our team will take a closer look.

  • +2 in reply to Michael Quirk

    From out engineering team:

    Modify the TCS file that you provided so that the outputs will be phase aligned by doing these adjustments.

    • DPLL0 is configured in DPLL mode, so it can lock to a reference in the future.
      • For locking to 1PPS, the DPLL settings will need to be different compared to locking to 10MHz.
      • For details on the lock to 1PPS settings, see Table 5 from the common use cases application note attached.
      • I can assist with providing register writes to change the settings if needed. Alternatively, I can provide separate configurations, one for 10MHz, another for 1PPS
    • Phase alignment is handled by the output TDC.
    • DPLL1 and DPLL2 are combo bus slaves of DPLL0, so frequency variations on DPLL0 are passed to DPLL1 and DPLL2
    • Output phase adjustments can be made using OUTPUT_0.OUT_PHASE_ADJ.OUT_PHASE_ADJ[31:0]. Which is a signed 32-bit phase adjustment in units of FOD cycles. This register is self triggering.

    • I have attached a copy of the device programming guide for customer reference

    8A3xxxx Family Programming Guide (v4.9) 20220525.pdf

    Timing_Commander_Cnfgs-Common-Use-v1.02-20240313.pdf

    Here is the modified .TCS file

    8A34001_output_do_not_sync_v2_JOC_March22_2024.zip

  • 0 in reply to Michael Quirk

    Thank you for the quick support. The outputs are aligned and coarse phase adjust is working, so is duty cycle adjustment.
    We will know work on the fine phase adjustments.

    The intermediate clock at which the FOD is running shall always be 500 MHz.

    A list of register writes to switch between local reference crystal, external 10 MHz-Input and PPS input would be appreciated. Output clocks don't need to make clean transitions when switch. We will likely turn of the outputs when switching.

    Regards,

    Kolja

  • +1 in reply to Kolja

    From our engineering team:

    I noticed that I did not config the validation interval for the 1pps input so I made an update. Please see v3 of the freerun configuration. I also generated “lock top 1pps” and “lock to 10MHz” configurations, which are also attached should the customer desire them.

    Using the configurations and in internal tool, I have generated I2C sequences that can be used to switch between configurations. For example, “8A34001_20240326_103730_programming_lock_to_1pps_export_Generated_Output_I2C_1B_i2ctools.txt” contains the writes to switch to the lock to 1pps config when the device is programmed with the freerun config or lock to 10MHz config.

    Can you clarify what is meant by “The intermediate clock at which the FOD is running shall always be 500 MHz”? The FOD frequency in the configurations is currently 500.48MHz due to the 1.28MHz outputs.

    0564.Temp.zip

  • 0 in reply to Michael Quirk

    Thank you for your support. 

    For the experimental tests, we let the tools select the intermediated frequency. For the product it will stay constant at 500 MHz to simplify the updates when changing parameters.

    Once the coarse fine adjust was working, we quickly got the fine adjust configured using the output TDC phase offset parameter.