Hi,we want to use the 8a34001 system synchronizer in one of our new products. For evaluation we are experimenting with the evaluation board.
We can configure a lot of our desired settings successfully, but we fail to synchronise the output phase of two outputs derived from the same input clock with different FODs. The coarse phase offset between the two output seems to vary randomly between reconfigurations of the parameters.
Our assumption is that the output divders are not synchronised. But we do not understand what is necessary to do that.
The ultimate goal is to have to identical clocks with 10 MHz each that have a programmable phase offset between them.
Beside a short comment in the Timing Commander I could not find any documentation on how to reset the output dividers simultaneosly.
Do you have any tips for us how to do it?
We would also be willing to pay for an FAE to train us or provide a configuration to us.
Regards,
Kolja
Hi,
sorry for the late feedback, we can get the last example you sent to work on our 8A34001 evaluation board. Unfortunately, we cannot do the same on our own designed board. We tried to use the same config except for the different crystals we are using. We adapted the 001 config to use the same DPLLs to make the configs easier to compare. Unfortunately the SYSDPLL and DPLL4 are locked, but the output TDC never goes to the valid state. The phases of Q5-Q7 are drifting, sometimes stables for a couple of seconds. We already tried many approaches, tested all voltages. Applied the workaround mentioned in 4.8.8 release notes.
System APLL(c05d) 00, loss_sticky :0, loss_live:0
DPLL 4 (c058) 03, hold_over_state_change_sticky :0, lock_state_change_sticky:0, state: 3
REF 4 (c062) 12, INPUT: 12
DPLL 5 (c059) 00, hold_over_state_change_sticky :0, lock_state_change_sticky:0, state: 0
REF 5 (c063) 1f, INPUT: 1f
DPLL 6 (c05a) 00, hold_over_state_change_sticky :0, lock_state_change_sticky:0, state: 0
REF 6 (c064) 1f, INPUT: 1f
DPLL 7 (c05b) 00, hold_over_state_change_sticky :0, lock_state_change_sticky:0, state: 0
REF 7 (c065) 1f, INPUT: 1f
DPLL 8 (c05c) 03, hold_over_state_change_sticky :0, lock_state_change_sticky:0, state: 3
REF 8 (c066) 12, INPUT: 12
Output TDC Global(c0e8) 02, state:2
Output TDC 0 (c0e9) 02, valid :0, state: 2
Output TDC 1 (c0ea) 02, valid :0, state: 2
Output TDC 2 (c0eb) 02, valid :0, state: 2
Besides the two tcs files with the different configs, I have also attached a full dump of the register space.
Can you please provide us some hints, what we could check as a further step?
Engineering's Response:
To clarify, the configurations you provided use Q8-Q11. Q5-Q7 are not used, was this a typo or did you/the customer provide the wrong configurations by mistake?
I tested the two configuration files that you provided and I observe no issues with the output TDC of output alignment.
The DPLL and OTDC status values that the customer provided indicate the correct statuses. No sticky bits are raised with indicates no loss of lock.
ZIP file contains 3 files, but having issues posting this. I will try to send you private message with the ZIP file.
We finaly got to test your suggestions, unfortunatly it did not help.
Yes sorry, I meant the outputs of DPLL4-7 which are connected to Q8-Q11.
The output TDC is not set up how I would have expected. They could have used only OTDC0 with DPLL5,6,7 included in the output mask. While I do not see any issue on my setup, I have made this change to align with our typical practices. Please see the updated TCS files attached
We want to have different phase offsets for each output, this is the reason we are using separate output TDCs, we tested setting the offsets, but it has no effect until the output TDC are valid.
Since an TCXO//OCXO is used, it should be used as the output TDC reference clock instead of the XTAL. I have made this change in both configurations.
We tested this just now, unfortunately this did not have any effect (we also tried it before)CCC0: 00000000 00000000 00000000 00000000 d0 00000000 03000000 00000000 00000000Output TDC Global(c0e8) 02, state:2Output TDC 0 (c0e9) 02, valid :0, state: 2Output TDC 1 (c0ea) 00, valid :0, state: 0Output TDC 2 (c0eb) 00, valid :0, state: 0
The number of output TDC samples per adjustment was set to 2. Typically we use a value of 2 when the master divider of the channels being aligned is 1pps to avoid long times between adjustments. Since these configurations use a master divider frequency of 1.25MHz, we recommend using the max number of samples = 4096. I have made this change in both configurations.
Can you tell us which register you are talking about? The only related field we can find is:OUTPUT_TDC_0.OUTPUT_TDC_CTRL_0
SAMPLES[15:0]
R/W
0
Unsigned 16-bit value indicating the number of samples to use formeasurement.0 = 4096 samples.When using more than one sample, the final measurement is an average.
which is set to 0 , so should be the default 4096:CD00: 00000000 20240700The only diff we can see in the .tcs file is concerning this register:DPLL4_LOCK_PHASE_LOCK_MAX_ERROR: 0 -> 10we applied that as well.
I have updated the personality file for the configurations from v8.4.0 to the most recent v10.12.0. Personality files can be downloaded here:8A34001 TCP v10.12.0: https://www.renesas.com/us/en/document/swo/timing-commander-personality-file-clockmatrix-8a34001-v10120-fw488-fw496?r=4558668A34003 TCP v10.12.0: Attached with this comment
We are using the older version of Timing Commander (8.4.0), as this is the latest one, to support 4.8.7 which is currently on the 8A34003 chip. We will install an EEPROM and use the latest firmware in the next days.
How are these configurations being programmed to the device?What is the state of the device when these configurations are programmed? I.e, do they contain a different configuration when programmed or are they programmed after power cycle with no OTP config load?
We have a custom board with an RP2040 connected via USB.The chip is a -000 version and we never programmed any OTP on it.We trigger the configuration of the 8A34003 manually a long time after the power cycle, by resetting it and switching the chip to 2 byte addressing via SPIWe export the configuration for the 8A34003 as an I2C 2 byte address input file (modify the page address in the first line) and let the RP2040 write them via SPI.The SPI 2 byte address export in our timing commander does not work, this is why we use I2C export, we use the 2 byte addressing just that the file is legible.We currently have no driver to let Timing Commander access the 8A34003 and no example, how to program the firmware of the device.
I will feed this back to our engineering team for review / comment.