ClockMatrix Output Coarse Phase Alignment

Question

Hi, we want to use the 8a34001 system synchronizer in one of our new products. For evaluation we are experimenting with the evaluation board. 
 
 We can configure a lot of our desired settings successfully, but we fail to synchronise the output phase of two outputs derived from the same input clock with different FODs. The coarse phase offset between the two output seems to vary randomly between reconfigurations of the parameters. 
 Our assumption is that the output divders are not synchronised. But we do not understand what is necessary to do that. 
 The ultimate goal is to have to identical clocks with 10 MHz each that have a programmable phase offset between them. 
 Beside a short comment in the Timing Commander I could not find any documentation on how to reset the output dividers simultaneosly. 
 Do you have any tips for us how to do it? 
 We would also be willing to pay for an FAE to train us or provide a configuration to us. 
 Regards, 
 Kolja

Michael Quirk · Accepted Answer

From out engineering team: 
 
 Modify the TCS file that you provided so that the outputs will be phase aligned by doing these adjustments. 
 
 DPLL0 is configured in DPLL mode, so it can lock to a reference in the future.
 
 For locking to 1PPS, the DPLL settings will need to be different compared to locking to 10MHz. 
 For details on the lock to 1PPS settings, see Table 5 from the common use cases application note attached. 
 I can assist with providing register writes to change the settings if needed. Alternatively, I can provide separate configurations, one for 10MHz, another for 1PPS

Phase alignment is handled by the output TDC. 
 DPLL1 and DPLL2 are combo bus slaves of DPLL0, so frequency variations on DPLL0 are passed to DPLL1 and DPLL2 
 Output phase adjustments can be made using OUTPUT_0.OUT_PHASE_ADJ.OUT_PHASE_ADJ [31:0] . Which is a signed 32-bit phase adjustment in units of FOD cycles. This register is self triggering.

I have attached a copy of the device programming guide for customer reference 
 
 8A3xxxx Family Programming Guide (v4.9) 20220525.pdf 
 
 Timing_Commander_Cnfgs-Common-Use-v1.02-20240313.pdf 
 
 Here is the modified .TCS file 
 
 8A34001_output_do_not_sync_v2_JOC_March22_2024.zip

Michael Quirk · Answer

From our engineering team: 
 
 I noticed that I did not config the validation interval for the 1pps input so I made an update. Please see v3 of the freerun configuration. I also generated &ldquo;lock top 1pps&rdquo; and &ldquo;lock to 10MHz&rdquo; configurations, which are also attached should the customer desire them. 
 Using the configurations and in internal tool, I have generated I2C sequences that can be used to switch between configurations. For example, &ldquo;8A34001_20240326_103730_programming_lock_to_1pps_export_Generated_Output_I2C_1B_i2ctools.txt&rdquo; contains the writes to switch to the lock to 1pps config when the device is programmed with the freerun config or lock to 10MHz config. 
 Can you clarify what is meant by &ldquo; The intermediate clock at which the FOD is running shall always be 500 MHz &rdquo;? The FOD frequency in the configurations is currently 500.48MHz due to the 1.28MHz outputs. 
 0564.Temp.zip

Michael Quirk · Answer

Kolja, 
 For ClockMatrix, the firmware can be updated via the Timing Commander GUI. We normally deliver a 8A34003 with FW 4.8.8 so there is no need for a firmware update. The current TCP (Timing Commander Personality) on the web supports FW4.8.8 - Timing Commander Personality File for ClockMatrix 8A34001 (v10.12.0, FW4.8.8, FW4.9.6) . We only recommend that customer update to FW4.9.6 to use certain advanced features of the device which usually involve PWM to transfer TOD and clocks between CM devices. Most customers should stay with the FW delivered from the factory.

ClockMatrix Output Coarse Phase Alignment

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