Hello,
I have designed a custom test board for 8A34043 (Rev E) ClockMatrix chip based on the EVK schematics.
My target application is to re-synchronize Qx clock output on an asynchronous/random event on CLKx input by using SYNC PULSE feature. For this application, Qx output frequency may be 10 MHz.
I am using Timing Commander and I managed to output 10 MHz on Q8 nQ8 (differential LVPECL). I also configured Q9 at a random frequency of 100 kHz with a Duty Cycle of about 10% (100 ns high time). Then I tied Q9 output to CLK0 input.
Now I would like to configure Q8 in SYNC PULSE mode using CLK0 as reference but I can't find the proper configuration to do so... In what I understand, the "first" rising edge of Q8 will be re-aligned on each rising edge of CLK0?
I join you my current Timing Commander profile. Thanks in advance for the help.
Regards,
Loic
8A34043_20240625_041347.zip
Just to double check you are tying Q9 output to the input, correct?
SP mode requires two inputs. See app note.
REN_CM-Frame-Sync_APN_20210713.pdf
Hi Michael, thank you for your quick answer!
I think I have to give more details about my final application :
My goal is to build a (kind of) highly configurable delay line/pulse generator/retriggerable monostable to format the output of a sensor.
The sensor "randomly" triggers a comparator which generates a sharp pulse. When the comparator output goes high, I need to generate a pulse with a defined width, at a defined delay (both parameter needs to be adjusted in factory)
I had in mind to use a 1 GHz oscillator with an high speed binary counter and a bunch of ligic to do this, but it would result in a jitter of more or less 1 ns and a complex circuit.
Then I discovered the ClockMatrix chip with a SYNC PULSE feature which seemed very interesting. Plus the fact that frequency, duty cycle and phases are configurable.
I would only need to configure output frequency (period) and duty cycle of the ClockMatrix output to create a defined pulse shape (low state would match the delay, and high state would match the pulse width), and I'd only need a bunch of logic to keep only one period when the comparator is triggered. The duty cycle and frequency limitations would be a little tradeof regarding the complex function I need.
Btw, regarding the scheme of the SYNC PULSE feature, I think I misundestood something (two inputs needed) and dealing with asynchronous events (sensor detections) will be more challenging/impossible.
But as I already have a test circuit, I am still wanting to give it a try, but I'm a bit lost with the Application Note as 8A34043 Timing Commander interface has not all the CLKx inputs and Qx outputs than the given example, I'm trying to figure out what DPLL to assign to which CLK inputs and outputs.
Thank you and have a nice day.
Stand-by, we are checking on some things.
Applications team currently is back logged and is unable to support this at this time.