LOL signal of 8T49N241 frequency translator in synthesis mode & DBITM setting

Dear all,

I have a question regarding the LOL signal of the the 8T49N241 frequency translator which can be output via GPIO3. When using the device in synthesis/free-run mode without using the digital PLL, does this signal reflect the lock status of the analog PLL? The datasheet clearly states that the signal reflects the signal of the digital PLL but what confuses me is that for the Xilinx ZCU104 board, the signal is directly routed to the FPGA fabric and used as the "tx_refclk_rdy" signal for the video phy controller. When only using the TX capability, the 8T49N241 device is configured in free-run mode and, according to the datasheet, should therefore not generate a LOL signal.

My second question is about the DBITM setting in register 0x0069. According to the datasheet, this bit should have a default value of 0. In my case, it is 1 after reset. What does this setting (as well as VCOMAN and DBIT) do?

Best regards,

Jelle

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  • Hey Michael,

    I am happy to share my configuration but I don't see how it is related to my general questions:

    - Can the device generate a LOL signal on GPIO3 when in synthesizer mode?

    - What are the DBITM, VCOMAN and DBIT settings and what could be the reason for DBITM being '1' after reset despite its default value being '0' according to the datasheet?

    Please let me know if you still need my configuration.

    Best,

    Jelle

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