Zero Delay Buffer

The main feature of a Zero Delay Buffer is to bring the clock signal at the receiver phase aligned with the clock signal at the input buffer.

Example let’s just assume the skew is 0 and also SPO is 0. So remaining is a feedback path, different delay and output trace delay.

So if you increase, if you increase the feedback path, the phase will be even can be advanced, it happened before the input the clock input signal. If you reduce the feedback path the delay, it can add the delay to the other receiver. So user can adjust the phase link and the delay of the feedback. To adjust the phase, but there's a restriction between on the phase, on the phase delay on the feedback path is you cannot go over one clock.

The main feature of a Zero Delay Buffer is to bring the clock signal at the receiver phase aligned with the clock signal at the input buffer.

Example let’s just assume the skew is 0 and also SPO is 0. So remaining is a feedback path, different delay and output trace delay.

So if you increase, if you increase the feedback path, the phase will be even can be advanced, it happened before the input the clock input signal. If you reduce the feedback path the delay, it can add the delay to the other receiver. So user can adjust the phase link and the delay of the feedback. To adjust the phase, but there's a restriction between on the phase, on the phase delay on the feedback path is you cannot go over one clock.