Hi,
We have a custom board where we use a 5P49V6965 to generate HDMI tmds clock.We either synthesize a frequency from the vco fed by xtal reference, or we need to buffer clkin to out1.With the latter use case, we experience issues with some ICs, where we don't get a clock at all.Even though the pll/vco path isn't used when buffering clkin to out1, we can get the output clock to recover by re-calibrating the vco.-> Can you please explain in detail what the conditions are in which the output is muted?-> Is there a way to buffer the clock from clkin to out1 without having the calibrate the vco?Having to do so seems unnecessary and I would expect there to be a way to override the logic that mutes the clock.
Is it possible that ICs with different date codes have different conditions for muting the clock?Best regards,Bart Van Severen
Bart,
Would it be possible for you to provide your Timing Commander Project file (.tcs) and a portion of your schematic showing your setup around the device.
Normally, no there should not be a difference based on Date Code but please provide me with a Date code that works as you expect it to and one that does not.
Hi Michael,OK ICs are from Week 49 2021 and the NOK ICs from Week 18 2024.Context as requested:
I'm not using the timing commander, but a custom linux driver to configure the 5P49V6965.This is the procedure we use for switching from XTAL clock to CLKIN->OUT1:1. I2C must run from XTAL clock only to avoid I2C failure when switching to possibly mute CLKIN
0x18[0] = 1
2. Select reference clock: XTAL (freerun) / CLKIN (loopthrough)
assert CLKSEL gpio
3. Wait ~1000 µsecs
4. Enable refmode and disable ref doubler
0x10[6] = 1 (CLKIN)
0x10[3] = 0 (REFDOUBLER EN)
0x10[2] = 1 (REFMODE EN)
5. Set predivider to 3 (rationale: max HDMI clock 340 MHz / 3 < IDT5P49_PLLREF_MAX 150 MHz)
0x15 = 3
6. Enable predivider
0x16[7] = 0 (PREDIVIDER EN)
7. Set OUT1 mux so that OUT1 = CLKIN
0x21[3:0] = 0xC
I am going to have engineering review this and I will provide you with their feedback as soon as they get back to me. ( Internal ticket TECHSUPP-8240 )
From our engineering team:
I ordered a part from PNG with same date code “418XNN”. I generated a config file (with 148.5Mhz input to CLKIN and CLKINB and 148.5Mhz output) from TC. and programmed the config to it and get target 148.5Mhz output.
Could we ask customer to try to program with the register map attached, see if they could also get the target output? I also attached the I2C programming process log file for customer reference. config2_register_map_from_TC.txt Program_log_file.txt
Fullscreen config2_register_map_from_TC.txt Download Config 2 registers: 61 03 FF 00 00 00 00 00 00 FF FD 00 00 B6 B4 92 44 0C A1 A0 00 03 8C 01 10 00 00 00 9F FF F0 80 00 0C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7B 05 BB 04 BB 04 BB 04 FF 44
Config 2 registers: 61 03 FF 00 00 00 00 00 00 FF FD 00 00 B6 B4 92 44 0C A1 A0 00 03 8C 01 10 00 00 00 9F FF F0 80 00 0C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 7B 05 BB 04 BB 04 BB 04 FF 44
Fullscreen Program_log_file.txt Download 0000 01:12:24.50 [slave 0xD4] wr [a]6A-[data]00 00 00 00 80 [len: 6] 0001 01:12:24.50 [slave 0xD4] R0.6A rd 00 00 00 00 80 [len: 5] 0002 01:12:25.01 [slave 0xD4] wr [a]00-[data]61 03 FF 00 00 00 00 00 00 FF FD 00 00 B6 B4 92 44 0C A1 A0 00 03 8C 01 10 00 00 00 9F FF F0 80 [len: 33] 0003 01:12:25.03 [slave 0xD4] R0.00 rd 61 03 ff 00 00 00 00 00 00 ff fd 00 00 b6 b4 92 44 0c a1 a0 00 03 8c 01 10 00 00 00 9f ff f0 80 [len: 32] 0004 01:12:25.03 [slave 0xD4] wr [a]20-[data]00 0C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [len: 33] 0005 01:12:25.04 [slave 0xD4] R0.20 rd 00 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [len: 32] 0006 01:12:25.04 [slave 0xD4] wr [a]40-[data]80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [len: 33] 0007 01:12:25.06 [slave 0xD4] R0.40 rd 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [len: 32] 0008 01:12:25.06 [slave 0xD4] wr [a]60-[data]7B 05 BB 04 BB 04 BB 04 FF 44 [len: 11] 0009 01:12:25.06 [slave 0xD4] R0.60 rd 7b 05 bb 04 bb 04 bb 04 ff 44 [len: 10] 0010 01:12:25.07 [slave 0xD4] R0.76 rd e3 [len: 1] 0011 01:12:25.07 [slave 0xD4] wr [a]76-[data]C3 [len: 2] 0012 01:12:25.07 [slave 0xD4] wr [a]76-[data]E3 [len: 2] 0013 01:12:25.18 [slave 0xD4] R0.1C rd 9f [len: 1] 0014 01:12:25.18 [slave 0xD4] wr [a]1C-[data]1F [len: 2] 0015 01:12:25.18 [slave 0xD4] wr [a]1C-[data]9F [len: 2]
0000 01:12:24.50 [slave 0xD4] wr [a]6A-[data]00 00 00 00 80 [len: 6] 0001 01:12:24.50 [slave 0xD4] R0.6A rd 00 00 00 00 80 [len: 5] 0002 01:12:25.01 [slave 0xD4] wr [a]00-[data]61 03 FF 00 00 00 00 00 00 FF FD 00 00 B6 B4 92 44 0C A1 A0 00 03 8C 01 10 00 00 00 9F FF F0 80 [len: 33] 0003 01:12:25.03 [slave 0xD4] R0.00 rd 61 03 ff 00 00 00 00 00 00 ff fd 00 00 b6 b4 92 44 0c a1 a0 00 03 8c 01 10 00 00 00 9f ff f0 80 [len: 32] 0004 01:12:25.03 [slave 0xD4] wr [a]20-[data]00 0C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [len: 33] 0005 01:12:25.04 [slave 0xD4] R0.20 rd 00 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [len: 32] 0006 01:12:25.04 [slave 0xD4] wr [a]40-[data]80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [len: 33] 0007 01:12:25.06 [slave 0xD4] R0.40 rd 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [len: 32] 0008 01:12:25.06 [slave 0xD4] wr [a]60-[data]7B 05 BB 04 BB 04 BB 04 FF 44 [len: 11] 0009 01:12:25.06 [slave 0xD4] R0.60 rd 7b 05 bb 04 bb 04 bb 04 ff 44 [len: 10] 0010 01:12:25.07 [slave 0xD4] R0.76 rd e3 [len: 1] 0011 01:12:25.07 [slave 0xD4] wr [a]76-[data]C3 [len: 2] 0012 01:12:25.07 [slave 0xD4] wr [a]76-[data]E3 [len: 2] 0013 01:12:25.18 [slave 0xD4] R0.1C rd 9f [len: 1] 0014 01:12:25.18 [slave 0xD4] wr [a]1C-[data]1F [len: 2] 0015 01:12:25.18 [slave 0xD4] wr [a]1C-[data]9F [len: 2]
Hi Michael,Thx for your answer, I'll try that Tuesday, which is the earliest possibility for me.At first glance, the difference is that 0x16[7] = 1, so the predivider is bypassed.I'll let you know if that fixes the problem and if it works on both "good" and "bad" ICs.Best regards,Bart Van Severen
Keep me updated
Hi Michael,Forgot to mention, but I also see that vco is calibrated at the end.That's what I now also do to recover the output clock.So that brings me back to my original question: -> Is there a way to buffer the clock from clkin to out1 without having the calibrate the vco?Best regards,Bart Van Severen
I don't think so, but I will confirm that with our engineering team.
if using CLKIN/CLKIN_B, they can have the correct signal at OUT1/OU1B by triggering VCO recalibration (setting register 0x1C from 0x1F to 0x9F).
Hi Michael,
As expected, vco recalibration is necessary and confirm that works.Any update on why vco recalibration was not needed with ICs from Week 49 2021?Best regards,Bart Van Severen