When writing interrupt handlers, it is obviously necessary to clear bit 16 of IESLR[] to prevent the handler routine running over and over again, but is there an easy way of knowing which IESLR register needs its 16th bit cleared?
In the configuration tab for setting up interrupts, does the automatically generated code take care of setting the relevant bits ins ISER[0] to enable the interrupts?
Ian said:Where are these functions documented? I have done a text search of the FSP manual and drawn a blank.
When you generate code , search in 'ra' folder, in your project in e2studio
Ian said:In the configuration tab for setting up interrupts, does the automatically generated code take care of setting the relevant bits ins ISER[0] to enable the interrupts?
mostly yes, but it depends in the complex hardware . Like in timer in PTP , there are driver functions which lets you enable IRQ on rising or falling edge. You can also check OPEN or ENABLE driver calls to verify this. On serial port drivers interrupts are configured by drivers. You can however select priority and callback function in GUI.
Ian said:When writing interrupt handlers, it is obviously necessary to clear bit 16 of IESLR[] to prevent the handler routine running over and over again, but is there an easy way of knowing which IESLR register needs its 16th bit cleared?
When you configure interrupt in IDE it also shows ISR names, if you look for the code , you will find out that flags are cleared at the end using
R_BSP_IrqStatusClear(irq);
IRQn_Type irq = R_FSP_CurrentIrqGet();
Where are these functions documented? I have done a text search of the FSP manual and drawn a blank.