Currently I can not load my program into the FLASH or RAM memory for one of the DA14683 MCUs used. After investigating the problem, I found that the J-Link debug probe can not find the CoreSight components in the ROM table.
Following CoreSight components are missing:-> SCS (System Control Space)-> DWT (Data Watchpoint and Trace)-> FPB (Flash Patch and Breakpoint)
Is there a way to restore or find the missing CoreSight components?
Terminal output connecting the MCU with the J-Link debug probe using JLinkeExe:--------------------------------------------------------------------------------------------------------------
SEGGER J-Link Commander V7.56b (Compiled Oct 18 2021 16:35:20) DLL version V7.56b, compiled Oct 18 2021 16:35:03 Connecting to J-Link via USB...O.K. Firmware: J-Link V9 compiled May 7 2021 16:26:12 Hardware version: V9.60 S/N: xxxxxxxx License(s): RDI, GDB, FlashDL, FlashBP, JFlash VTref=1.819V Type "connect" to establish a target connection, '?' for help J-Link>con Please specify device / core. <Default>: CORTEX-M4 Type '?' for selection dialog Device>CORTEX-M0 Please specify target interface: J) JTAG (Default) S) SWD T) cJTAG TIF>S Specify target interface speed [kHz]. <Default>: 4000 kHz Speed> Device "CORTEX-M0" selected. Connecting to target via SWD Found SW-DP with ID 0x0BB11477 DPIDR: 0x0BB11477 Scanning AP map to find all available APs AP[1]: Stopped AP scan as end of AP map has been reached AP[0]: AHB-AP (IDR: 0x04770021) Iterating through AP map to find AHB-AP to use AP[0]: Core found AP[0]: AHB-AP ROM base: 0xE00FF000 CPUID register: 0x410CC200. Implementer code: 0x41 (ARM) Found Cortex-M0 r0p0, Little endian. FPUnit: 0 code (BP) slots and 0 literal slots CoreSight components: ROMTbl[0] @ E00FF000 Cortex-M0 identified. J-Link>
For comparison the terminal output of a working DA14683 MCU.-------------------------------------------------------------------------------------
SEGGER J-Link Commander V7.56b (Compiled Oct 18 2021 16:35:20) DLL version V7.56b, compiled Oct 18 2021 16:35:03 Connecting to J-Link via USB...O.K. Firmware: J-Link V9 compiled May 7 2021 16:26:12 Hardware version: V9.60 S/N: xxxxxxxx License(s): RDI, GDB, FlashDL, FlashBP, JFlash VTref=1.828V Type "connect" to establish a target connection, '?' for help J-Link>con Please specify device / core. <Default>: CORTEX-M4 Type '?' for selection dialog Device>CORTEX-M0 Please specify target interface: J) JTAG (Default) S) SWD T) cJTAG TIF>S Specify target interface speed [kHz]. <Default>: 4000 kHz Speed> Device "CORTEX-M0" selected. Connecting to target via SWD Found SW-DP with ID 0x0BB11477 DPIDR: 0x0BB11477 Scanning AP map to find all available APs AP[1]: Stopped AP scan as end of AP map has been reached AP[0]: AHB-AP (IDR: 0x04770021) Iterating through AP map to find AHB-AP to use AP[0]: Core found AP[0]: AHB-AP ROM base: 0xE00FF000 CPUID register: 0x410CC200. Implementer code: 0x41 (ARM) Found Cortex-M0 r0p0, Little endian. FPUnit: 4 code (BP) slots and 0 literal slots CoreSight components: ROMTbl[0] @ E00FF000 [0][0]: E000E000 CID B105E00D PID 000BB008 SCS [0][1]: E0001000 CID B105E00D PID 000BB00A DWT [0][2]: E0002000 CID B105E00D PID 000BB00B FPB Cortex-M0 identified. J-Link>
Hi There,
Thanks for your question. Is this a custom board, or any of our EVKs?
Can you please share the GDBSetver configuration that you are using?
I would suggest to install a previous JLink version (e.g. v5.xx) as described in the following UM : https://www.renesas.com/in/en/document/mas/um-b-044-da1468x-software-platform-reference?language=en&r=1600761
Regards,
PM_Renesas
My apologies for the late reply. I've been busy with other work related tasks.
I am using a custom board.
In the following you can find my gdbserver configurations:JLinkGDBServerCLExe -device Cortex-M0 -if SWD -speed 1000 -port 2331 -singlerun
Like you suggested I downgraded my JLink software, but to no avail. The downgraded JLink produced the same error pattern as before.
Additionally, I want to emphasis, that I currently have access to multiple identical custom boards supporting the DA14683. The outlined problem only arises with one of the custom boards. As a result of the portrayed circumstances, I don't think the problem is due to a configuration mistake. For me the more plausible problem cause is a corrupt CoreSight ROM table. Is there a way to restore or reconfigure the CoreSight ROM table?
Is the QSPI flash empty or not? If not, can you please try to erase it using UART? You can use the python scripts from SmartSnippets Studio.
As far as I know, it's not possible to restore the CoreSight. To check this internally and deeply, I would like to understand the procedure you followed in order to get this error during programming. Can you please share more insights?