DA14531 (WLCSP17) Cannot flash external SPI (or read OTP) - Failed clearing memory address 7FC3C08. Failed configuring SPI ports and pins.

Question

Question 
 How can we let SmartSnippets Toolbox turn off HW_RESET, or otherwise customize the jtag_programmer.bin ? 
 Context 
 We have been able to run our firmware (based on the ble_app_example, for SDK version: 6.0.14.1114) using Keil - so we know we can program the RAM fine. 
 However, once we try and use our external SPI flash we run into an error. 
 Looking at the scope traces of the chips Boost voltage (BAT_HIGH), we believe it is because the HW_RESET is left enabled, the voltage boosts from 1.8V to 3V for 10ms before crashing to the supply of 1.5V and then raising back to 1.8V. 
 We were able to fix this issue (when running from RAM) by adding the following to the start of our code: 
 
 GPIO_Disable_HW_Reset (); 
 
 But now we are seeing the same behaviour in our boost voltage when programming with SmartSnippets, we think this is because the jtag_programmer.bin (that is flashed first) needs modifying in the same way. 
 We have a custom board where we are reusing various pins, due to pin constrains we cannot turn on the SPI flash via a GPIO, but are using a suitable configuration to be under the 50uA limit for the BAT_HIGH pin.

DA14531 Pin 
 Assigned Pin

P0_4 
 SPIB_SCK

P0_1 
 SPIB_CS

P0_3 
 SPIB_MISO

P0_0 / RST 
 SPIB_MOSI

P0_5 
 SWDIO (JTAG)

P0_2 
 SWCLK (JTAG)

However when trying to use the SmartSnippets Toolbox or command line we run into the following 
 [ERROR SPI Flash Programmer@23-03-21 12:13:20] Failed reading memory at address 0x7FC3C08. [WARNING SPI Flash Programmer@23-03-21 12:13:20] Failed configuring SPI ports and pins. 
 
 Command line arguments used (powershell) 
 
 & 'C:\Program Files\SmartSnippetsToolbox\SmartSnippetsToolbox5.0.22\SmartSnippetsToolbox.exe' -type spi -chip DA14531 -clk P0_4 -cs P0_1 -miso P0_3 -mosi P0_0 -jtag 601004718 -cmd write -offset 0x0000 -file "C:\Projects\da14531-firmware\Keil_5\out_DA14531\Objects\fwa_531.bin" -max 0x400000 -firmware "C:\Projects\da14531-firmware\sdk\config	oolbox_resources\DA1453x\common\jtag_programmer.bin" -bootable

Full Output:

Launching SmartSnippets Toolbox v5.0.22.4084 
 Loaded the following properties from C:\Users\CDP\SmartSnippetsToolbox\properties.txt 
 {ENABLE_HIDDEN_TOOLS=true, ENABLE_TS=true, ENABLE_MP=false, ENABLE_TE=true} 
 Command line arguments: 
 -type spi -chip DA14531 -clk P0_4 -cs P0_1 -miso P0_3 -mosi P0_0 -jtag 601004718 -cmd write -offset 0x0000 -file C:\Projects\da14531-firmware\Keil_5\out_DA14531\Objects\fw_531.bin -max 0x400000 -firmware C:\Projects\da14531-firmware\sdk\config	oolbox_resources\DA1453x\common\jtag_programmer.bin -bootable 
 Found SW-DP with ID 0x0BC11477 
 Scanning AP map to find all available APs 
 AP[1]: Stopped AP scan as end of AP map has been reached 
 AP[0]: AHB-AP (IDR: 0x04770031) 
 Iterating through AP map to find AHB-AP to use 
 AP[0]: Core found 
 AP[0]: AHB-AP ROM base: 0xE00FF000 
 CPUID register: 0x410CC601. Implementer code: 0x41 (ARM) 
 Found Cortex-M0 r0p1, Little endian. 
 FPUnit: 4 code (BP) slots and 0 literal slots 
 CoreSight components: 
 ROMTbl[0] @ E00FF000 
 ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB008 SCS 
 ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 000BB00A DWT 
 ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 000BB00B FPB 
 BTLE device selected. 
 Found SW-DP with ID 0x0BC11477 
 AP map detection skipped. Manually configured AP map found. 
 AP[0]: AHB-AP (IDR: Not set) 
 AP[0]: Core found 
 AP[0]: AHB-AP ROM base: 0xE00FF000 
 CPUID register: 0x410CC601. Implementer code: 0x41 (ARM) 
 Found Cortex-M0 r0p1, Little endian. 
 FPUnit: 4 code (BP) slots and 0 literal slots 
 CoreSight components: 
 ROMTbl[0] @ E00FF000 
 ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB008 SCS 
 ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 000BB00A DWT 
 ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 000BB00B FPB 
 Reset: Halt core after reset via DEMCR.VC_CORERESET. 
 Reset: Reset device via AIRCR.SYSRESETREQ. 
 Firmware File C:\Projects\da14531-firmware\sdk\config	oolbox_resources\DA1453x\common\jtag_programmer.bin has been selected for downloading. 
 Reset: Halt core after reset via DEMCR.VC_CORERESET. 
 Reset: Reset device via AIRCR.SYSRESETREQ. 
 Reset: Halt core after reset via DEMCR.VC_CORERESET. 
 Reset: Reset device via AIRCR.SYSRESETREQ. 
 Successfully downloaded firmware file to the board. 
 Using default baudrate: 115200 Bd. 
 Added bootable header to image. 
 Started burning memory with 20764 bytes of data at address 0x00000. 
 Failed clearing memory address 7FC3C08. 
 Failed configuring SPI ports and pins. 
 Failed clearing memory address 7FC3C08. 
 Fail write 16384 bytes at offset 0x00 
 Memory burning failed.

Update 2023/03/22 
 When using the SmartSnippets toolbox (GUI) I am also unable to read the OTP memory. I can confirm I am able to use the GUI tool to read the OTP memory of the devboard kit.

CDP · Accepted Answer

Extremely grateful for your help OV_Renesas. 
 
 I wanted to share a summary of the ticket resolution here for any future readers. 
 Fixing OTP memory read 
 The issue regarding reading OTP memory was fixed by using the dev-board as a J-Link 
 We followed the instructions here: 
 http://lpccs-docs.renesas.com/Tutorial_SDK6/debug_probe.html#da14531-pro-development-kit 
 Then we observed that we could read the SPI flash (without any special changes)! 
 But had some trouble writing the flash. 
 We are seeing the following error (messages for burning and then erasing): 
 
 [INFO Flash Code@23-03-27 13:26:29] Started burning memory with 21396 bytes of data at address 0x00.
[ERROR SPI Flash Programmer@23-03-27 13:26:29] Adddittional error info at JTAG address 0x7FC3C0C. (MSB first): FF FF FF F8.
[ERROR Flash Code@23-03-27 13:26:29] Fail write 16384 bytes at offset 0x00
[ERROR Flash Code@23-03-27 13:26:29] Failed burning memory.
[INFO Flash Code@23-03-27 13:27:33] Started erasing from 0x00 to 0x5394 (6 sectors)
[ERROR Flash Code@23-03-27 13:27:33] Memory erasing failed. 
 At this point we had disabled the HW_RESET in the flash_programmer and therefore we re-enabled this. We then made more progress. 
 When we read the SPI Flash this way we actually see that it is partially flashed correctly. ie some of the bits match, but the whole image we want burned does not seem to have been sent across. 
 When we try and Burn the SPI flash using this method, we get the following error: 
 [INFO Flash Code@23-03-27 13:32:57] Started burning memory with 21396 bytes of data at address 0x00.
[ERROR SPI Flash Programmer@23-03-27 13:32:57] Failed reading memory at address 0x7FC3C08.
[ERROR Flash Code@23-03-27 13:32:57] Fail write 16384 bytes at offset 0x00
[ERROR Flash Code@23-03-27 13:32:57] Failed burning memory. 
 Fixing the SPI Read & Burn Issue 
 This was our process for Burning & Erasing the SPI using with the SmartSnippets toolbox: 
 
 Hit "Connect" in GUI 
 Use the command line to read OTP and pass a custom ` -firmare ` flag, so we provide our custom build & 'C:\Program Files\SmartSnippetsToolbox\SmartSnippetsToolbox5.0.22\SmartSnippetsToolbox.exe' -type otp -chip DA14531 -jtag 480072116 -baudrate 57600 -cmd read_header -file "$env:USERPROFILE\Downloads\header.hex" -firmware "C:\Projects\Aramis\e4-da14531-sdk\utilities\flash_programmer\out_DA14531_JTAG\Objects\jtag_programmer_531.bin" -y 
 Use the GUI to "Read" and "Flash Code" and then also try "Burn" and "Erase"

As mentioned by OV_Renesas above: https://community.renesas.com/wireles-connectivity/f/bluetooth-low-energy/30177/da14531-wlcsp17-cannot-flash-external-spi-or-read-otp---failed-clearing-memory-address-7fc3c08-failed-configuring-spi-ports-and-pins/104499#104499 
 We needed to modify the flash_programmer image to include the additional SPI wait time. 
 We simply changed the #undef to a #define 
 /* Enable extra wait time after release from Ultra Deep Power-Down (UDPD). Mainly required for the */
/* Adesto/Dialog SPI flash memories which support the UDPD command. */
/****************************************************************************************************************/
-#undef CFG_SPI_FLASH_ADESTO_UDPD
+#define CFG_SPI_FLASH_ADESTO_UDPD
 
 The summary of the flash_programmer build: 
 
 #define CFG_SPI_FLASH_ADESTO_UDPD 
 Ensure that #define CFG_HW_RESET_P00 is used (default behaviour, but I mentioned earlier in this question I disabled it, that was not required) 
 
 The summary of our custom firmware build: 
 
 We kept the HW_RESET enabled & with a state where the SWD pins were enabled for debug ( DA14531 cannot reuse JTAG SWDIO or SCLK pins as GPIO with pull-up/pull-down ? (blinky demo) - Bluetooth Low Energy - Wireless Connectivity - Renesas Community ). This allowed us to reprogram the board with a RAM program, so we could reflash the flash_programmer and then reprogram the SPI Flash .

Additional Notes 
 For our purposes we didn't need to access the SPI flash in our custom firmware (only for booting), so we didn't need to make some of the changes the flash_programmer in our custom firmware too. 
 For this SPI chip we were lucky and didn't need to flash the secondary bootloader. 
 
 As OV_Renesas provided in the support ticker: 
 In order to be able to read/write/erase the SPI Flash via SW as well in your FW you will have to update the spi_flash.h file as well. For instance, for P25Q11U which is the integrated SPI Flash on the DA14531MOD: 
 // P25Q11U
#define P25Q11U_MAN_DEV_ID 0x8510
#define P25Q11U_JEDEC_ID 0x854011
#define P25Q11U_CHIP_SIZE 0x20000
#define P25Q11U_MEM_PROT_UPPER_HALF 4
#define P25Q11U_MEM_PROT_LOWER_HALF 36
#define P25Q11U_MEM_PROT_ALL 8
/// Device index of supported SPI flash memories
typedef enum
{
 /// W25x10CL device index
 W25X10CL_DEV_INDEX = 1,

 /// W25x20CL device index
 W25X20CL_DEV_INDEX,

 /// AT25DN011/AT25DF011 device index
 AT25DX011_DEV_INDEX,

 /// MX25V1006E device index
 MX25V1006E_DEV_INDEX,

 /// MX25R1035F device index
 MX25R1035F_DEV_INDEX,

 /// MX25R2035F device index
 MX25R2035F_DEV_INDEX,

 /// MX25R4035F device index
 MX25R4035F_DEV_INDEX,

 /// MX25R8035F device index
 MX25R8035F_DEV_INDEX,

 /// MX25R1635F device index
 MX25R1635F_DEV_INDEX,

 /// MX25V1035F device index
 MX25V1035F_DEV_INDEX,

 /// MX25V2035F device index
 MX25V2035F_DEV_INDEX,

 /// MX25V4035F device index
 MX25V4035F_DEV_INDEX,

 /// MX25V8035F device index
 MX25V8035F_DEV_INDEX,

 /// MX25V1635F device index
 MX25V1635F_DEV_INDEX,

 /// P25Q10U device index
 P25Q10U_DEV_INDEX,

 P25Q11U_DEV_INDEX,

 /// P25Q40U device index
 P25Q40U_DEV_INDEX,

 /// GD25WD10 device index
 GD25WD10_DEV_INDEX,

 /// GD25WD20 device index
 GD25WD20_DEV_INDEX,

 /// AT25DF021A device index
 AT25DF021A_DEV_INDEX,

 /// AT25EU0021A device index
 AT25EU0021A_DEV_INDEX,

 /// AT25XE041D device index
 AT25XE041D_DEV_INDEX,

 /// AT45DB081E device index
 AT45DB081E_DEV_INDEX,
} spi_flash_dev_index_t; 
 
 And on spi_flash.c file: 
 int8_t spi_flash_auto_detect(uint8_t *dev_id)
{
 int8_t status;
 // List of known SPI Flash devices
 const spi_flash_cfg_t known_spi_devs_list[] =
 {
 {W25X10CL_DEV_INDEX, W25X10CL_JEDEC_ID, W25X10CL_CHIP_SIZE},
 {W25X20CL_DEV_INDEX, W25X20CL_JEDEC_ID, W25X20CL_CHIP_SIZE},
 {AT25DX011_DEV_INDEX, AT25DX011_JEDEC_ID, AT25DX011_CHIP_SIZE},
 {MX25V1006E_DEV_INDEX, MX25V1006E_JEDEC_ID, MX25V1006E_CHIP_SIZE},
 {MX25R1035F_DEV_INDEX, MX25R1035F_JEDEC_ID, MX25R1035F_CHIP_SIZE},
 {MX25R2035F_DEV_INDEX, MX25R2035F_JEDEC_ID, MX25R2035F_CHIP_SIZE},
 {P25Q10U_DEV_INDEX, P25Q10U_JEDEC_ID, P25Q10U_CHIP_SIZE},
 {P25Q11U_DEV_INDEX, P25Q11U_JEDEC_ID, P25Q11U_CHIP_SIZE},
 {GD25WD20_DEV_INDEX, GD25WD20_JEDEC_ID, GD25WD20_CHIP_SIZE},
 {AT25DF021A_DEV_INDEX, AT25DF021A_JEDEC_ID, AT25DF021A_CHIP_SIZE},
 {AT25EU0021A_DEV_INDEX, AT25EU0021A_JEDEC_ID, AT25EU0021A_CHIP_SIZE},
 {AT25XE041D_DEV_INDEX, AT25XE041D_JEDEC_ID, AT25XE041D_CHIP_SIZE},
#if defined (__FPGA__)
 {MX25R8035F_DEV_INDEX, MX25R8035F_JEDEC_ID, MX25R8035F_CHIP_SIZE},
 {AT45DB081E_DEV_INDEX, AT45DB081E_JEDEC_ID, AT45DB081E_CHIP_SIZE},
#endif
 };
.
.
. 
 So, you should define the appropriate macros according to the AT25DF041B datasheet, insert your device on the spi_flash_dev_index_t and save it on the known_spi_devs_list as well. According to the AT25DF041B datasheet:

OV_Renesas · Answer

Hi There,

Thank you for posting your question online.
Can you share the external SPI Flash you are working on? You can find the supported SPI Flash modules for DA14531 on the AN-B-088 document:AN-B-088: DA145xx Flash Selector Guide (renesas.com)
You should also refer to the AN-B-072 document: AN-B-072: DA14531 Booting from OTP and Serial Interfaces (renesas.com)
On chapter 4.Booting Sequence and Booting Pins you can find this table:

The pins you have selected are for SPI slave. If you want to use a combination of pins not highlighted on this table you should configure the secondary_bootloader or you should burn the OTP System Preferences header accordingly.
The PIN configuration you have selected, is the default one. So you do not need to configure the SPI pins via CLI.
Can you please try a CLI command on the powershell that would look like this:

SmartSnippetsToolbox.exe -type spi -chip DA14531 -jtag JTAG_ID -firmware "jtag_programmer_531.bin" -cmd write -file *bin/hex file location" -verify

Your JTAG pins are correct according to the DA14531 Datasheet, since you were able to download from the Keil IDE to the DA14531 RAM as well.

Kind Regards,
OV_Renesas

OV_Renesas · Answer

Hi There, Thank you for the reply. Not being able to burn the SPI Flash is expected due to the fact you are using the AT25DF041B SPI Flash. But you should be able to read the OTP memory. What command did you try for OTP? This is my logs when burning the SPI Flash with the prox_reporter: C:\Program Files\SmartSnippetsToolbox\SmartSnippetsToolbox5.0.20>SmartSnippetsToolbox.exe -type spi -chip DA14531 -jtag 480071870 -firmware "jtag_programmer_531.bin" -cmd write -file prox_reporter_531.hex -verify
Launching SmartSnippets Toolbox v5.0.20.4060
Loaded the following properties from C:\Users\ovasinio\SmartSnippetsToolbox\properties.txt
{ENABLE_HIDDEN_TOOLS=true, ENABLE_TS=true, ENABLE_MP=true, ENABLE_TE=true}
Command line arguments:
-type spi -chip DA14531 -jtag 480071870 -firmware jtag_programmer_531.bin -cmd write -file prox_reporter_531.hex -verify
Found SW-DP with ID 0x0BC11477
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x04770031)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410CC601. Implementer code: 0x41 (ARM)
Found Cortex-M0 r0p1, Little endian.
FPUnit: 4 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB008 SCS
ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 000BB00A DWT
ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 000BB00B FPB
BTLE device selected.
Found SW-DP with ID 0x0BC11477
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410CC601. Implementer code: 0x41 (ARM)
Found Cortex-M0 r0p1, Little endian.
FPUnit: 4 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB008 SCS
ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 000BB00A DWT
ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 000BB00B FPB
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Firmware File jtag_programmer_531.bin has been selected for downloading.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Successfully downloaded firmware file to the board.
Using default baudrate: 115200 Bd.
Do you want SPI Flash memory to be bootable? ([Y / N]?)
y
Added bootable header to image.
Started burning memory with 29752 bytes of data at address 0x00000.
Successfully configured SPI ports and pins.
Write 16384 bytes at offset 0x00
Write 13368 bytes at offset 0x4000
Memory burning completed successfully.
Reading memory to verify its contents after burn...
Read 16384 bytes from offset 0x00
Read 13368 bytes from offset 0x4000
SPI Flash memory verification succeeded.
Send reset command. If application won't start replug the board. After that I was able to see my DA14531 advertising. And for reading the OTP header: C:\Program Files\SmartSnippetsToolbox\SmartSnippetsToolbox5.0.20>SmartSnippetsToolbox.exe -type otp -chip DA14531 -jtag 480071870 -firmware "jtag_programmer_531.bin" -cmd read_header -file otp_read.txt -y
Launching SmartSnippets Toolbox v5.0.20.4060
Loaded the following properties from C:\Users\ovasinio\SmartSnippetsToolbox\properties.txt
{ENABLE_HIDDEN_TOOLS=true, ENABLE_TS=true, ENABLE_MP=true, ENABLE_TE=true}
Command line arguments:
-type otp -chip DA14531 -jtag 480071870 -firmware jtag_programmer_531.bin -cmd read_header -file otp_read.txt -y
Found SW-DP with ID 0x0BC11477
Scanning AP map to find all available APs
AP[1]: Stopped AP scan as end of AP map has been reached
AP[0]: AHB-AP (IDR: 0x04770031)
Iterating through AP map to find AHB-AP to use
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410CC601. Implementer code: 0x41 (ARM)
Found Cortex-M0 r0p1, Little endian.
FPUnit: 4 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB008 SCS
ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 000BB00A DWT
ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 000BB00B FPB
BTLE device selected.
Found SW-DP with ID 0x0BC11477
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[0]: Core found
AP[0]: AHB-AP ROM base: 0xE00FF000
CPUID register: 0x410CC601. Implementer code: 0x41 (ARM)
Found Cortex-M0 r0p1, Little endian.
FPUnit: 4 code (BP) slots and 0 literal slots
CoreSight components:
ROMTbl[0] @ E00FF000
ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB008 SCS
ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 000BB00A DWT
ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 000BB00B FPB
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Firmware File jtag_programmer_531.bin has been selected for downloading.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Reset: Halt core after reset via DEMCR.VC_CORERESET.
Reset: Reset device via AIRCR.SYSRESETREQ.
Successfully downloaded firmware file to the board.
Using default baudrate: 115200 Bd.
Memory contents exported successfully to otp_read.txt
Reading is complete. Read 304 bytes. I had created the otp_read.txt file and after reading the OTP header I can see: So it worked as expected. Regarding the AT25DF041B Flash Memory: The AT25DF041B has a Ultra-Deep Power-Down (UDPD) mode, which takes more time to wake-up the device than the one the DA14531 BootROM supports. That is why you will have to use the secondary_bootloader. If you go on sdk_path\utilities\secondary_bootloader You will find the secondary_bootloader project. You will need to find and define the macro: 
/****************************************************************************************************************/
/* Enable extra wait time after release from Ultra Deep Power-Down (UDPD). Mainly required for the */
/* Adesto/Dialog SPI flash memories which support the UDPD command. */
/****************************************************************************************************************/
#undef CFG_SPI_FLASH_ADESTO_UDPD 
 You could burn this secondary_bootloader into the OTP in order to use it to download your FW into the AT25DF041B Flas Memory, or you could use J-link to connect to the AT25DF041B, burn the secondary_bootloader and then use CLI commands/ SmartSnippets Toolbox to burn your FW into the Flash. Kind Regards, OV_Renesas

DA14531 (WLCSP17) Cannot flash external SPI (or read OTP) - Failed clearing memory address 7FC3C08. Failed configuring SPI ports and pins.

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Update 2023/03/22

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