code flash issue

Question

Hi , 
 We have designed the custom board using DA14531 SOC and observed some issues while programming the board. I can able to detect the SOC but failing when i try to program it with smart snipet tool box. Please find the below screenshot for your reference.

Device is detecting. 
 
 please suggest. 
 
 Thanks in advance 
 Pavan S K

OV_Renesas · Answer

Hi Pavan,

Thank you for posting your question on our Online Engineering Community.
From the Schematic you have shared I can see that you are using the correct (default) SPI pins for the Flash and the correct (P0_2 and P0_10) pins for the SWD interface. Since it is a custom board, I suppose that you are working with J-link probes?
Could you try to hook your custom board SWD pins with the SWD pins on the Dev Kit?
Please refer here: 19. Serial Wire Debug Probe — DA145XX Tutorial SDK Getting started (renesas.com)
Try to connect and program your board via the J-Link available on the Dev Kit and share your feedback.

Kind Regards,
OV_Renesas

OV_Renesas · Answer

Hi Pavan,

Thank you for the reply and apologies for the delay.
I think the issue resides on the FW of the J-link Device/Probes.
From what you have shared on your initial post:

What I can see in Keil IDE:

The J-link OB firmware is different than the J-link firmware.
Please refer on the SEGGER site for information regarding J-link OB:

However, when you used the SWD interface of the DA14531 Dev Kit you should be able to download FW into the RAM via Keil or download FW into the Flash via the SmartSnippets Toolbox/ SmartBond Flash Programmer Tools.
Since you are using the AT25DF011 SPI Flash, have you configured it to work with UDPD? On the AT25DF011 Datasheet, you can find the UDPD specification:

Please refer on this ticket as well for more information regarding the AT25DF011 SPI Flash with UDPD enabled and how to program and boot from it: DA14531 (WLCSP17) Cannot flash external SPI (or read OTP) - Failed clearing memory address 7FC3C08. Failed configuring SPI ports and pins. - Bluetooth Low Energy - Wireless Connectivity - Renesas Community
According to the Schematic files you shared on a previous answer I can see this implementation for the AT25DF011 SPI Flash:

Is there a reason you are keeping the CS pin active high and connected into the Vcc?
According to the AT25DF011 Datasheet, the Chip Select (CS) pin should be able to change from high to low:

Also, the RST pin is the HOLD pin according to the datasheet.

Kind Regards,
OV_Renesas

OV_Renesas · Answer

Hi Pavan, Thank you for the reply. You should be able to change the clock settings via the tools SEGGER provides. Unfortunately, I cannot help you with that. You should reach out to Segger. You are using the correct Pins from the J-link EDU. Where do you connect the VTref? The J-Link uses the voltage between VDD and GND (VTref) as reference voltage for the communication. From the schematic you have shared you are supplying your chip with 3.3V but you are working with Buck Mode, which according to AN-B-075 : So on VTref you should connect the VDD_IO which is from 1.8V up to 3V at max. Kind Regards, OV_Renesas

OV_Renesas · Answer

Hi PSK, Apologies for the delay. Our HW team did not see much improvements in the layout. Do you face any issues when you try to implement our suggestions? 
 Schematic 
 
 R13 only makes sense, if they would like to decide later to run in buck or bypass mode. 
 There is no type number for Z9 and Y1. Are those components fitting to our spec? 
 Which serial interface is used to control the 531 in direct test mode? 
 
 Layout 
 
 There is still a gap in the reference ground for the RF trace. 
 The grounding on the bottom layer below the 531 is cut. 
 RF ground pins should not be connected on the top layer with analog/digital ground pins (see AN-B-075) 
 The external components of the DCDC converter should not couple the DCDC noise into sensitive traces. There is some risk of coupling into XTAL32Mm. 
 The routing of VCC_3.3V is not optimal. it should not run under the 32MHz xtal pins and the RF port. 
 C2 should be as close as possible to pin 5 (VBAT_LOW). 
 
 Kind regards, OV_Renesas