code flash issue

Hi Pavan,

Thank you for posting your question on our Online Engineering Community.
From the Schematic you have shared I can see that you are using the correct (default) SPI pins for the Flash and the correct (P0_2 and P0_10) pins for the SWD interface. Since it is a custom board, I suppose that you are working with J-link probes?
Could you try to hook your custom board SWD pins with the SWD pins on the Dev Kit?
Please refer here: 19. Serial Wire Debug Probe — DA145XX Tutorial SDK Getting started (renesas.com)
Try to connect and program your board via the J-Link available on the Dev Kit and share your feedback.

Kind Regards,
OV_Renesas

Hi ,

Thanks for your answer , I tried with the Devkit Jlink but issue still the same, not able to detect the device.

Please suggest.

Hi,

Waiting for your reply.

Thanks in advance

PSK

Hi Pavan,

Thank you for the reply.
So, you are not able to access the custom board by SWD or 1-Wire UART ?
Are you able to download any FW into the RAM via Keil IDE?
Also on P0_10 and P0_2 which are the SWD interface you have added the R5 and R3 resistors, which is their value and why did you add them?
Another approach, would be to remove all the peripherals (not the SPI Flash) and try to see if you are able to access the board.
Also where is TP1 which P0_5 is connected to?

Kind Regards,
OV_Renesas

Hi,

- Yes i can be able to download the firmware via Keil into the RAM, cannot debug.

-  R5 and R3 are 0E resistors just shorted.

- TP1 is unused we are not using.

Please suggest

Thanks in advance

PSK

Hi,

Getting below error while running in Keil.

Thanks in advance

Pavan s k

Hi ,

Waiting for your response. 

Thanks in advance

PSK

Hi Pavan,

Thank you for the reply and apologies for the delay.
I think the issue resides on the FW of the J-link Device/Probes.
From what you have shared on your initial post:

What I can see in Keil IDE:

The J-link OB firmware is different than the J-link firmware. 
Please refer on the SEGGER site for information regarding J-link OB:

However, when you used the SWD interface of the DA14531 Dev Kit you should be able to download FW into the RAM via Keil or download FW into the Flash via the SmartSnippets Toolbox/ SmartBond Flash Programmer Tools.
Since you are using the AT25DF011 SPI Flash, have you configured it to work with UDPD? On the AT25DF011 Datasheet, you can find the UDPD specification:

Please refer on this ticket as well for more information regarding the AT25DF011 SPI Flash with UDPD enabled and how to program and boot from it: DA14531 (WLCSP17) Cannot flash external SPI (or read OTP) - Failed clearing memory address 7FC3C08. Failed configuring SPI ports and pins. - Bluetooth Low Energy - Wireless Connectivity - Renesas Community
According to the Schematic files you shared on a previous answer I can see this implementation for the AT25DF011 SPI Flash:

Is there a reason you are keeping the CS pin active high and connected into the Vcc?
According to the AT25DF011 Datasheet, the Chip Select (CS) pin should be able to change from high to low:

Also, the RST pin is the HOLD pin according to the datasheet.


Kind Regards,
OV_Renesas

Hi ,

I obseved two thing I can able to flash to the chip using DA14531 USB KIT to both RAM and Flash, But unable to flas using DA14531 EVK kit.

Please suggest what might be the issue and what needs to be done.

Thanks in advance 

PSK

Hi Pavan,

Thank you for the reply.
Glad you are able to program your DA14531 custom board via the USB kit. 
Are you following this configuration for the DA14531 EVK kit:

You should be able to program your custom board with the SEGGER- EDU you have as well. 
What is the Max Clock you have set for J-link Segger EDU? Which pins have you connected into your custom board?

Kind Regards,
OV_Renesas

Hi ,

I tried with above configuration only, but not able program the board through DA14531 EVK, below are the screenshots for jlink setting when i connect with EVK. Please suggest.

Also where i can set the Clock and how to set for Jlink EDU please suggest.

we are using below pins,

Thanks in advance

psk

Hi Pavan,

Thank you for the reply.
You should be able to change the clock settings via the tools SEGGER provides. Unfortunately, I cannot help you with that. You should reach out to Segger. 
You are using the correct Pins from the J-link EDU.  Where do you connect the VTref? 
The J-Link uses the voltage between VDD and GND (VTref) as reference voltage for the communication. From the schematic you have shared you are supplying your chip with 3.3V but you are working with Buck Mode, which according to AN-B-075:




So on VTref you should connect the VDD_IO which is from 1.8V up to 3V at max.

Kind Regards,
OV_Renesas

Hi Pavan,

Thank you for the reply.
You should be able to change the clock settings via the tools SEGGER provides. Unfortunately, I cannot help you with that. You should reach out to Segger. 
You are using the correct Pins from the J-link EDU.  Where do you connect the VTref? 
The J-Link uses the voltage between VDD and GND (VTref) as reference voltage for the communication. From the schematic you have shared you are supplying your chip with 3.3V but you are working with Buck Mode, which according to AN-B-075:




So on VTref you should connect the VDD_IO which is from 1.8V up to 3V at max.

Kind Regards,
OV_Renesas

Hi ,

I tried with giving 3V only but no change. Couyld you please shall i use DA14695 USB kit to program da14531 SOC? If yes please share the details.

Thanks in advance

PSK

Hi There,

Thank you for the reply.
You had stated that you were able to flash your board with the USB Dev Kit DA14531, so why do you want to use the DA14695 USB kit ?

Kind Regards,
OV_Renesas

Hi ,

We have only one in stock , customer has only DA14695 kit, that the reason. Since DA14531 EVK not working.

Thanks in advance
PSK

Hi Pavan,

Could you kindly answer the questions below so we can get a better idea of what is going on with your board.
1. I suppose you have a Daughterboard for the Development Kit Pro as well.
Could you please program this Daughterboard with the ble_app_barebone example from the SDK? 
Please program it via JTAG and share if you are able to see it advertising. 
2. You stated that you were able to program your custom board via JTAG with the USB Dev Kit. 
Which firmware have you got into your custom board? Are you able to see your device advertising or is it constantly resetting? 
3. Have you tried this on different custom boards or only on a specific board?
4. You stated:

pk said:

Yes i can be able to download the firmware via Keil into the RAM, cannot debug.

This is not possible. In order to download firmware via Keil into the RAM, the debugger must be attached, so why are you not able to debug? Can you share via screenshots the steps you are following on the Keil IDE?
5. Could you please attach a logic analyzer on the SPI pins while you try to program your board and share the results?
6. In the Schematic review, we asked you to expose the P0_5 so you are able to access your board via 1-Wire UART. Have you tried to access the board via 1-Wire UART?


Kind Regards,
OV_Renesas

Hi ,

We have modified the board design , Please find the attached files review and give your valuable feedback. Hop the programming related issues will be resolved in this version of board. BLE TMPS Schematic.pdfBLE TPMS PCB R2 Gerber.zipRequest you to consider this on potential.

Thanks in advance

PSK

Hi ,

Waiting for your response.

Thanks in advance

PSK

Hi PSK,

Thank you for the reply.
We are currently working on this and I will get back to you as soon as possible.

Kind Regards,
OV_Renesas

Hi PSK,

Apologies for the delay.
Our HW team did not see much improvements in the layout. Do you face any issues when you try to implement our suggestions?

Schematic

• R13 only makes sense, if they would like to decide later to run in buck or bypass mode.
• There is no type number for Z9 and Y1. Are those components fitting to our spec?
• Which serial interface is used to control the 531 in direct test mode?

Layout

• There is still a gap in the reference ground for the RF trace.
• The grounding on the bottom layer below the 531 is cut.
• RF ground pins should not be connected on the top layer with analog/digital ground pins (see AN-B-075)
• The external components of the DCDC converter should not couple the DCDC noise into sensitive traces. There is some risk of coupling into XTAL32Mm.
• The routing of VCC_3.3V is not optimal. it should not run under the 32MHz xtal pins and the RF port.
• C2 should be as close as possible to pin 5 (VBAT_LOW).

Kind regards,
OV_Renesas