SCIx.BRR and SCI.xMDDR

Hi,

I have RX64M renesas and I am trying to understand how to configure BRR and MDRR with different bit rate (9600, 38400, 115200....)
So I need to understand the formula because when I use the formula in manual the value obtained is different.

Below there is the auto generated code:

void R_SCI0_Create(void)
{
/* Cancel SCI0 module stop state */
MSTP(SCI0) = 0U;

/* Set interrupt priority */
IPR(SCI0, RXI0) = _0F_SCI_PRIORITY_LEVEL15;
IPR(SCI0, TXI0) = _0F_SCI_PRIORITY_LEVEL15;

/* Clear the control register */
SCI0.SCR.BYTE = 0x00U;

/* Set clock enable */
SCI0.SCR.BYTE = _01_SCI_INTERNAL_SCK_OUTPUT;

/* Clear the SIMR1.IICM, SPMR.CKPH, and CKPOL bit, and set SPMR */
SCI0.SIMR1.BIT.IICM = 0U;
SCI0.SPMR.BYTE = _00_SCI_RTS | _00_SCI_CLOCK_NOT_INVERTED | _00_SCI_CLOCK_NOT_DELAYED;

/* Set control registers */
SCI0.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | _00_SCI_PARITY_EVEN | _00_SCI_PARITY_DISABLE |
_00_SCI_DATA_LENGTH_8 | _00_SCI_MULTI_PROCESSOR_DISABLE | _00_SCI_ASYNCHRONOUS_MODE;
SCI0.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_INVERT_NONE | _00_SCI_DATA_LSB_FIRST |
_10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT;
SCI0.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | _20_SCI_NOISE_FILTER_ENABLE | _10_SCI_8_BASE_CLOCK |
_40_SCI_BAUDRATE_DOUBLE | _04_SCI_BIT_MODULATION_ENABLE;
SCI0.SNFR.BYTE = _00_SCI_ASYNC_DIV_1;

/* Set bitrate */
SCI0.BRR = 0xB0U;
SCI0.MDDR = 0xE8U;

/* Set RXD0 pin */
MPC.P21PFS.BYTE = 0x0AU;
PORT2.PMR.BYTE |= 0x02U;

/* Set TXD0 pin */
PORT3.PODR.BYTE |= 0x04U;
MPC.P32PFS.BYTE = 0x0BU;
PORT3.PMR.BYTE |= 0x04U;
PORT3.PDR.BYTE |= 0x04U;

/* Set SCK0 pin */
MPC.P34PFS.BYTE = 0x0BU;
PORT3.PMR.BYTE |= 0x10U;
}

I need to know what is the new value when for example I change the bit rate from 38400 to 115200

Br,

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