We are programming the clock the first time. Phase noise tested is 10dB worse than the phase noise shown in datasheet for region from 1MHz offset and above (outside the PLL loop). What could be wrong? Also notice your plot has 15dBm output. Did you use external amplifier?
This issue is not in the private Technical support system and this thread is closed.
Would you be so kind as to upload your .TCS file for our engineering teams to review this issue.
Also, please tell me the exact device you are using.
100MHz 3.3V LVDS
Will try to get you the file. Thank you.
I can't upload the .tcs for some reason.
In that case it would be best to do this through our support ticketing system
Please submit a ticket and you can upload the file in this process.